This invention relates to the manufacture of semiconductor devices, and in particular to pads for planarization by mechanical polishing of dielectric layers formed over components in the manufacture of semiconductor devices.
During the manufacture of semiconductor devices, it is advantageous to provide a planarized surface for the purpose of avoiding problems, such as non-uniform resist exposure, associated with lithography on the non-planar surface of the wafer. Planarization is commonly achieved by providing a planarizing layer over a topographical surface which is a dielectric substance. The dielectric substance may be, for example, a spin-on-glass. Such planarizing layers generally provide a high degree of planarization for periodic features which are approximately 10 microns or smaller. Such small, repeating features are referred to as high-frequency features. However, such planarizing layers provide relatively poor planarization for underlying features having large periodicity. Rather, the upper surface of the planarizing layer tends to reflect the topography of the underlying structures. Such large features, also referred to as low-frequency features, may be, for example, separated by characteristic distances of 1 millimeter or more. Consequently, polishing techniques, ordinarily using a rotating soft pad and a fluid or slurry between the pad and the surface, are employed to obtain long-range planarization where the underlying features are spatially large.
However, such polishing techniques are not entirely successful. When the underlying structures are repeating, the surface of the dielectric has a regular periodic waveform. Regions of high-frequency features are separated by regions of few or no features in some devices. This type of topography leads to a wave-like dielectric surface after planarization. Soft pads begin to become ineffective in planarizing features having periodicities on the order of about 100 microns and greater. Various structures, such as interconnects, when randomly routed on devices such as gate arrays, can have periodicities in excess of 1 millimeter. In VLSI devices, large separations between features are encountered, especially in the peripheral areas of the device. The height of an oxide on a wafer for memory chips may have a high point in the arrays of each chip and a low point at or in the vicinity of the scribe line between dies. The period of such variation in height may thus be as much as 5 millimeters, especially between die on a wafer. Conventional soft pads, as noted above, are not effective in planarization over such distances. Thus, conventional soft pads are not effective in planarization of dielectric layers formed over interconnects with large periodicities greater than approximately 100 microns.
Wafer surfaces are not generally perfectly planar. Rather, wafers have thickness variations and warp or bow. As a result, a rigid planar polishing pad would also fail to provide a uniform planarizing layer for use. For example, a rigid planar polishing pad may provide a substantially planar surface in one region of a wafer, while, in other regions of the wafer, because of non-uniformities in the wafer, it removes an excessive amount of the thick planarizing layer and even damages the underlying structures.
Use of a rigid planar polishing pad also requires that the pad surface and the wafer surface be maintained effectively parallel to one another essentially over the whole wafer area. If the surfaces are not parallel, different amounts of the thick planarizing layer may be removed from different regions of the wafer. Consequently, there may be a failure to remove enough material to planarize some sections of the wafer. In other sections of the wafer, the thick planarizing layer may be made too thin, and underlying structures may also be damaged by the rigid pad.
Objects and advantages of the invention will become apparent from the detailed description of a preferred embodiment which follows.